1. Technical Field
The present invention relates to a multilayered substrate, a semiconductor unit having a multilayered semiconductor, and an electronic unit using the same.
2. Background Art
With a reduction in the size and an increase in functions of recent electronic units, there have been an ongoing increase in pins and speed and an ongoing trend of high-speed transmission, in semiconductor devices constituting electronic units. A package having semiconductor devices mounted and a large number of passive parts are mounted on printed substrates used for the electronic equipment. Many of these passive parts are capacitor elements. Many of the capacitors are used to smoothen switching noises superposed by supply voltage. These capacitors are also used as de-coupling capacitors, which prevent high-frequency noises generated in a processor from flowing out across the entire printed substrate. The capacitors are also used to prevent voltage drop through the quick supply of much current after a switchover in the operating mode of the processor. To play their role effectively, it is an indispensable condition that these capacitors should reduce the value of equivalent series inductance (ESL). To reduce the ESL, a large number of capacitors are usually wired and mounted in parallel. Stacked ceramic chip capacitors are often used as these capacitor elements. However, ceramic capacitors suffer from a substantial capacity reduction if bias voltage is superposed or if the operating environment of ceramic capacitors reaches high temperatures.
As a measure for reducing power supply noises resulting from semiconductor devices mounted on the electronic unit described above, it is known to mount capacitor elements as close to semiconductor devices as possible. It has been therefore proposed that built-in capacitor elements should be provided in interposer substrates that constitute a semiconductor package. Substrates having built-in chip capacitors are disclosed, for example, in Japanese Patent Unexamined Publication No. 2001-185460 and JP-A-11-220262. As disclosed in Japanese Patent No. 2738590, other multilayered substrates are proposed, where capacitor elements function as de-coupling capacitors, positively utilizing dielectric layers held between conductive foils as capacitive layers. Meanwhile, a case is disclosed in JP-A-10-97952 and Japanese Patent Unexamined Publication 2002-359160, where built-in sheet capacitors such as aluminum electrolytic capacitors having a large capacity are provided in printed substrates.
As multilayered substrates used in packages, glass-epoxy multilayered substrates as shown in FIG. 10 are widely used. Glass-epoxy multilayered substrate 55 is composed of insulating layer 50 having epoxy resin impregnated and hardened in a glass woven fabric as a reinforcing material and wiring pattern 51 formed on both sides of insulating layer 50. Wiring pattern 51 is composed of a copper foil and insulating layer 50 is also formed on wiring pattern 51. Through holes 52 are formed in glass-epoxy multilayered substrate 55 and copper layers 53 are formed inside walls of through holes 52 by a plating technique. Wiring pattern 54, which is composed of a copper foil, is formed on the top layer of glass-epoxy multilayered substrate 55. Glass-epoxy multilayered substrate 55 is also called a multilayered substrate formed through a plated through hole technique. Multilayered substrates formed through a plated through hole technique can be mass produced at low cost, being very widely used as interposer substrates as well. If, in addition, semiconductor devices 56 are mounted by a wire bonding technique, multilayered substrates formed by the aforementioned plated through hole technique are often used.
If semiconductor devices are mounted through flip chip mounting, where semiconductor devices are connected through wiring-layer pad electrodes and solder bumps or Au bumps, wiring with higher density is demanded. Therefore, buildup multilayered printed substrates (hereinafter, referred to as “buildup substrates”) using a buildup technique have also been developed. Buildup substrates are formed by using a glass-epoxy multilayered substrate as a core substrate, building up insulating layers on the core substrate, which have wiring patterns formed, and connecting wiring patterns between upper and lower layers by means of a via. On buildup substrates, connections can be made through a via at necessary points between upper-layer and lower-layer wiring patterns, thus reducing space for the connecting via. As a result, this makes it possible to reduce the diameter of the via and make line widths and intervals microscopic. Therefore, high-density wiring can be realized. Vias, used to make connections between layers on the buildup substrate, are usually formed by plating. However, buildup substrates have been developed where vias are formed using conductive paste without using plating. For example, ALIVH (registered trademark) and B2 it are available as buildup substrates using conductive paste, which have no core substrate and all layers are built up.
To improve the electrical properties of an electronic unit including semiconductor devices of interest, it is necessary to mount a large number of capacitor elements including de-coupling capacitors on a printed substrate. The large number of parts makes it difficult to reduce the size and cost of electronic units.
As shown in FIG. 10, semiconductor packages using glass-epoxy multilayered substrates and wire bonding mounting, currently used widely, do not require much attention to the length of wiring including wires if these packages are used in applications where semiconductors operate at speeds of 100 MHz or less. However, semiconductor packages where large amounts of information need be transmitted as semiconductors used for imaging systems do require a large number of noise-preventing capacitors to be mounted for proper operation. Therefore, these semiconductor packages have a large number of parts. For de-coupling capacitors mounted on mother boards, for example, efforts are made to reduce equivalent series inductance (ESL) by connecting a large number of de-coupling capacitors in parallel. Therefore, a large number of parts are inevitably used. If, in addition, chip capacitors formed by sintering ceramic are used as de-coupling capacitors, a large number of de-coupling capacitors need to be mounted, taking the temperature characteristics of capacitive values into consideration.
As a measure for reducing power supply noises resulting from semiconductor devices, it has also been proposed that built-in capacitor elements should be provided on interposer substrates, which constitute a semiconductor package, aiming to form capacitive elements as close to semiconductor devices as possible. As disclosed in Japanese Patent No. 2738590, for example, a multi-layered substrate has been proposed where dielectric layers made of resin material, which are held between conductive foils, are positively used as capacitive layers and function as de-coupling capacitors. With this construction, however, the capacitive layers are made of resin and have a few tens of levels of relative permittivity, which makes it impossible to form a large-capacity capacitor. Therefore, the above-mentioned type of de-coupling capacitor has a de-coupling function, but cannot store sufficient charges to serve to smoothen noises such as switching noises superposed by supply voltage or prevent voltage drop through the quick supply of much current after a switchover in the operating mode of the processor. In other words, there is a limit to this type of de-coupling capacitors if thought is given to how many parts help to reduce noises. If, in addition, semiconductors operate faster, an interposer substrate having built-in capacitor elements ends up being an interposer with built-in capacitors that is incapable of addressing a challenge of more stable supply voltage. If, in addition, a plurality of electrodes exist in a single flat dielectric layer, the use of one power supply system is not problematic. However, the use of a plurality of power supply systems will raise a problem that individual power supply noises propagate through dielectric layers.
As means for providing built-in large-capacity capacitors, a construction where built-in chip capacitors are used is therefore available, as disclosed in JP-A-11-220262. Chip-capacitor electrodes are usually on the same plane and it is necessary to form a power-supply electrode and a grounding electrode of a substrate built-in on the same plane. Normally, a power layer and a grounding layer are often on different layers. Thus, there is a problem that a substantial design change is requested so that built-in chip capacitors are provided.
It has also been proposed, as disclosed in Japanese Patent Unexamined Publication No. 2001-185460, that built-in capacitors can be provided using spaces between power layers and grounding layers by mounting chip capacitors vertically. Even in this case, however, a design change around chip parts is inevitable, which remains problematic. In addition, the vertical burial and mounting of chip parts raise a problem that the thickness between the power layer and the grounding layer is 0.6 mm even if small 0603-size (unit: mm) chips are used, thus resulting in a thick interposer substrate itself.
It has also been proposed, as disclosed in JP-A-10-97952 and Japanese Patent Unexamined Publication No. 2002-35916, that a single built-in aluminum electrolytic capacitor is provided on a substrate as means for providing a relatively thin large-capacity built-in capacitor element. However, it is thought as a prerequisite that the use of the built-in aluminum electrolytic capacitor necessitates a design change for an interposer.